Introduction
An overview of the evolutionary migration from DDR to DDR2 to DDR3 will be covered, including the timeframe from start of standardization efforts to production. The broad range of DDR3-related standards will be summarized covering memory devices, support devices, modules, interfaces and packaging standards - with participating JEDEC committees identified. The JEDEC standardization process will be reviewed, including the extensive use of task groups to complete the detailed analysis and document creation efforts.
Presented by Mian Quddus, Samsung and JEDEC Chairman

Why Migrate to DDR3?
A customer-based overview will be provided summarizing the processor/bandwidth/performance and density needs that were that led to the DDR3 production definition. An overview of the performance, features and functional improvements with DDR3 will be shown, in an effort to help memory users determine if/when a migration to DDR3 is appropriate.
Presented by Geof Findley, Intel

Specific examples will be shown of designs using the new DDR3 packages, for illustrative purposes.
Presented by Rich Parent, Nanya

Lunch

DDR3 Initialization Sequence & Reset
This session will cover the DDR3 initialization sequence, including power supply ramp, device initialization, warm boot, an overview of the mode registers and the memory device state diagram. Examples of actual system power-on situations will be covered, including historical system power supply ramp and/or initialization failures and some design considerations to avoid such problems in new designs. The presentation will provide further insight into the memory device, bus and system operations taking place during the memory power-up process.
Presented by DY Lee, Samsung

DDR3 Write/Read Leveling
The read and write leveling operation will be introduced for DDR3, including why the function is needed (based on example system wiring topologies, flight times, etc) and the limiting affect on memory operating frequency if this new feature is not used. Real-life single and multi-rank memory subsystem examples will be used to demonstrate the need, operation and benefit of the new feature in maximizing the useful operating frequency of DDR3 in new applications. On-die termination will be introduced, as well as the MPR (multi-purpose register) and key device timing parameters associated with write and read leveling.
Presented by DY Lee, Samsung

Break

DDR3 ODT & Dynamic ODT
The DDR3 on-die termination function will be reviewed, including a description and rationale for the function, ODT control modes, synchronous ODT, asynchronous ODT and dynamic ODT. Extensive memory subsystem examples will be used, at a range of operating speeds, bus structures (pt-to-pt, multi-drop, fly-by, etc) and drive conditions. Key ODT timing parameters, mode register settings and ODT functionality during various memory operations will be covered. Timing diagrams and simulation results will allow attendees to comprehend the benefits of the ODT feature when properly applied to various applications ranging from on-board to multi-rank.
Presented by Todd Farrell, Micron Technology

DDR3 Timings, Input/Output Specifications, Etc.
This session will round-out the DDR3 specification overview by describing the AC and DC specifications/reference loads for the new technology, in addition power management, frequency change procedures, optional features such as DLL on/off, ASR, extended temperature operation, clock jitter specifications, capacitance specifications, etc.

The presentation will offer a greater understanding and the rationale behind the selected values, interpretation of the values (including the reference loads), measurement methods and common system problems associated with failures to meet theses values. In addition, DDR3 functions not previously covered will be described, ensuring that all major attributes of the technology are understood.
Presented by Todd Farrell, Micron Technology

DDR3 Interface Review and Design Considerations
This session will cover a broad range of DDR3 interface specifications and provide real-world examples (net structures, simulation waveforms) and demonstrate the application of specification de-ratings that may apply for various waveforms. Topics will include driver and receiver characteristics, ZQ calibration (short/long), driver sensitivity (temp/voltage), set-up and hold time specifications, de-rating based on slew rates and/or non-linear transitions, etc.

Through the use of real-world examples and simulations, the DDR3 interface specifications will be shown to enable operation using various net structures over the full DDR3 operating range - when available programmable features are properly applied. This session will further suggest optimal net structures, data eye measurement methods and interface timing calculation methods (timing budgets) to ensure adequate operational margins.
Presented by William Shen, Qimonda

Lunch

1:00 pm -
2:00 pm

Planned/available raw card designs will be reviewed for each module family, with available gerber file designs and Design Specifications summarized. An overview of the support devices such as PLL's, registers and AMB devices will be shown, as well as an overview of the SPD's and the SPD revision methodology planned for the DDR3 generation. The material will also include a review of some of the design considerations for the major module families, including net topologies, cross-sections/board impedances and signal referencing - with the expectation that this information may be useful both to module and non-module applications.
Presented by Takao Ono, Elpida

Information will be shown regarding JEDEC publications and how to locate specifications on the JEDEC site, including a review of how JEDEC member companies can access all memory-related meeting presentations and pre-publication documents.
Presented by Mark Kellogg, Program Chair, JEDEC